High-speed printer

ABSTRACT

A high-speed printer of the dot matrix type in which incoming information to be printed, presented in either serial or parallel form, is examined for invalid bits and loaded into a buffer in parallel fashion. Printing does not begin until the buffer is loaded to print a line of the desired length. Printing begins as soon as the first character loaded into the buffer reaches the output stage at which time the actuation of the print wires of the dot matrix are moved across the paper document at a substantially constant speed. Detection of the location of the carriage assembly moving the printer head assembly is performed independent of the movement of the carriage to actuate the print wires at the appropriate locations. Logical circuitry is provided for detecting the presence of invalid characters and the buffer and serial-to-parallel converter are cleared prior to the loading of the next group of characters to be printed on the next line of print. During serial transmission, the printer assembly generates Acknowledge signals to indicate to the transmitting facility that the previous character has been received and stored.

Filed Appl Assignee:

l'IIGH-SPEED PRINTER [72] Inventors: Robert Howard, Roslyn,

Prentice I. Robimon, Hudson; Herbert E. Menhennett, Windham, both of NH.

Centronics Data Computer Corporation, Hudson, NH.

: May 7, 1970 US. Cl ..197/1 R, 197/19, 340/l72.5 Int. Cl. ..B4lj 25/00Field of Search 197/1, 19, 20; 340/174 SR,

[ 1 Nov. 28, 1972 Primary Examiner-Edgar S. Burr Attorney-Ostrolenk,Faber, Gerb & Soffen ABSTRACT 340 1725 of the location of the carriageassembly moving the printer head assembly is performed independent ofthe movement of the carriage to actuate the print wires at [56]References Cited h l Lo a! d d t e appropriate ocatlons. g1c circultry1s prov! e UNITED STATES PATENTS for detecting the presence of invalidcharacters and 2,997,152 8/1961 Dirks ..197/1 R buffer andslmal'm'pamllel matter are prior to the loadmg of the next group ofcharacters to 3,232,403 2/1966 l-lebel ..197/19 be printed on the nextlme of print. During senal 3,260,341 7/1966 Braumg et al. ..197/19 t thbl t 3 300 017 1/1967 Yazejian et al 197/1 R e assem y i es 31 3 604/1967 Foster 01/122 Acknowledge s1gnals to indicate to the transmittmgu f that the haI te h be n i d 3,353,648 11/1967 Amada et a1 ..197/20 xif li Premus 6 ac as 6 race 3,405,392 10/1968 Milne et al. ..197/1 R X3,544,967 12/ 1970 Sallach et al. ..340/172.5 23 Clains, 23 DrawingFigures mu/Ez 521. fi i: DELEf 37 f; u/vs F550 get/"E F W ear; 1

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M CL 0 Z4q PATENTEDnuvze m2 SHEEI 010F12 PATENTED nnv 28 I972- SHEETU80F12 v mh y QM N PATENTEI'] NOV 28 m2 SHEET 07 0F 12 3.703.949 SHEETUSOF 12 PATENTEDnuvzsmz PATENTEDHDVZB I972 sum 10oF 12' PATENTED "UV 2 81972 saw 12m 12 HIGH-SPEED PRINTER The present invention relates toprinters and more particularly to a line printer of the dot matrix typefor performing a high-speed page printing.

Wire matrix printers are well known in the prior art. One of theearliest types of wire matrix printers is comprised of a plurality ofwires arranged in matrix fashion for making impact througha ribbon to apaper document whereby the wires are selectively energized to formcharacters, numerals and other symbols. The earliest type of wire matrixprinters were capable of printing either words or entire characters. Thenext development in the art consisted of wire matrix printers having aplurality of wires arranged in a M-row by N- column fashion. A typicalarrangement for such wire matrix printers are to provide a total of 35wires arranged in seven rows and five columns to print any character,number, or symbol. In operation, selected ones of the print wires aredriven against the paper document to form the desired character orsymbol. The print wires are then shifted one position to the right toprint the next character whereby shifting occurs in an intermittentfashion. Since 35 separate mechanisms must be provided for each of the35 print wires forming the 5 X 7 matrix, the amount of mass which mustbe moved to perform such printing is quite appreciable. This therebyresulted in the development of wire matrix type printers in which only 7print wires are employed. The print wires are typically arranged in avertical line and are selectively driven against the paper document toform one of the seven columns of the character. The carriage assemblywhich moves the print wire assembly is then shifted one position to theright to print the next column. This operation continues until all fivecolumns have been printed to ultimately form the character or othersymbol.

The present invention is characterized by providing a high speed impactprinter of the dot matrix type in which the printer head assembly isconstantly moved across the paper document at speeds not heretoforecapable of being achieved in present day systems.

The present invention is comprised of a carriage assembly which supportsa printer head assembly having solenoid driven print wires. The entireprinter head assembly, including the solenoid drivers, is moved acrossthe paper document at a constant rate of speed. The arrangement of theprinter head assembly is such as to provide a light weight compactstructure so as to minimize the mass which is moved across the paperdocument, enabling the structure to move at relatively high speed.

The carriage assembly is driven at a substantially constant rate ofspeed which is independent of the printing operation. The location ofthe carriage assembly is detected by a position readout device whichgenerates a pulse as the carriage assembly moves into the next printingposition regardless of the speed at which the carriage assembly is beingmoved.

A buffer is provided for storing all the characters to be printed upon asingle line, which buffer is fully loaded before printing begins. Sincethe buffer is purely an electronic solid state device, the printingspeed is limited only by the mechanical structure and not by the buffer.Each character is examined for validity before insertion into the bufferto prevent the loading of invalid characters. As soon as the buffer iseither fully loaded or loaded to the extent called for by thetransmitting facility, the printing operation is initiated. The printingoperation continues until an end of line signal is detected, at whichtime the buffer is automatically cleared, a dummy character is loadedinto the buffer and the carriage assembly is returned to itsleft-handmost position in readiness for the next line of print. The bitlengths of each character are detected for validity by a controlcounter. The state of each bit is determined by the duration in whichthe first portion of the bit interval is at a first level. A timingcounter is provided to examine the state of each binary bit comprising acharacter within a 20 microseconds interval to substantially reduce theeffect of any spurious signal upon the accuracy of the bit beingreceived. This arrangement provides a printer having a capability ofprinting more than 165 characters per second, for accepting serialinformation at a rate of better than 3,000 bits per second and iscapable of accepting up to 80,000 characters per second in the paralleltransmission mode providing an extremely high speed printer which isfurther capable of providing multiple original copies from the singleprinting operation.

It is, therefor, one object of the present invention to provide a novelhigh speed impact printer of the dot matrix type in which the printingoperation is independent of the speed of movement of the print carriage.

Still another object of the present invention is to provide a novel highspeed impact printer of the dot matrix type in which the print headassembly is moved at a constant rate of speed and printing is controlledby electronically detecting the position of the printer head assembly.

Still another object of the present invention is to provide a novel highspeed impact printer of the dot matrix type in which characters of eachline of print are loaded into a buffer before initiation of the printoperation in order to permit the print mode to be performed at a highrate of speed.

Still another object of the present invention is to pro- 7 vide a novelhigh speed impact printer of the dot matrix type in which characters ofeach line of print are loaded into a buffer before initiation of theprint operation in order to pennit the print mode to be performed at ahigh rate of speed and wherein characters are examined for validitybefore insertion into the buffer to prevent the loading of invalidcharacters.

Still another object of the present invention is to provide a novel highspeed impact printer of the dot matrix type in which characters of eachline of print are loaded into a buffer before initiation of the printoperation in order to permit the print mode to be performed at a highrate of speed and wherein characters are examined for validity beforeinsertion into the buffer to prevent the loading of invalid charactersand wherein the bufier is automatically clear and loaded with a dummycharacter prior to the receipt of the next group of characters to beprinted as the next line of print.

These as well as other objects of the present invention will becomeapparent when reading the accompanying description and drawings inwhich:

FIG. 1 shows a block diagram of a printer system incorporating theprinciples of the present invention.

FIG. 2 shows the same of the dot matrix type characters generated by theprinter of H6. 1.

FIG. 3 is a logical diagram showing the .timing counter employed in thesystem of FIG. 1 in greater detail.

FIG. 4 is a logical diagram showing the control counter employed in thesystem of FIG. 1 in greater detail.

FIGS. 5-52: are timing diagrams showing various waveforms developed bythe circuitry of the present invention, which waveforms are useful inunderstanding the operation of the present invention.

FIG. 6 is a logical diagram showing the serial-toparallel inputconverter employed in the system of FIG. 1 in greater detail.

FIGS. 7a-7c and 8a-8f are logical diagrams showing the error detectionand decoding circuitry respectively employed to controlsome of theoperating functions of the system of FIG. 1.

FIGS. 9a-9c are logical diagrams showing the decoding circuitry employedfor controlling mechanical functions of the system of FIG. 1.

FIGS. 10:: and 10b are logical diagrams showing the buffer and theposition locating decoding circuitry and character generator matrix ofFIG. 1 in greater detail.

FIG. 11 shows the position detecting apparatus of FIG. 1 in greaterdetail.

GENERAL SYSTEM DESCRIPTION FIG. 1 shows one preferred embodiment of thesystem of the present invention in block diagram form, which system 10is comprised of an input line 11 for receiving the binary information inserial fashion from a computer which is adapted to generate a serialpulse train in which groups of pulses represent the characters to beprinted. In the present preferred embodiment, each character (i.e.,number, letter or symbol) is represented by a six-bit binary code whichprovides a total of 64 different binary combinations, each onerepresenting a specific number, letter or symbol. The six binary bitsare generated (by a computeror other transmitting facility) and areapplied to input terminal 1 1 which, in turn, transfers the serialinformation to the input of a serial-to-parallel converter circuit 13.The input bufferv l3 converts the serial information applied to it intoparallel form and further acts as a means for isolating the inputinformation from register 15.

The serial-to-parallel converter circuit 13 is a shift register whichreceives each of the six binary data bits (plus a stop and start bit)comprising each character in serial fashion and shifts each bit to thenext succeeding stage of the shift register until the entire characteris loaded into register 13. Input timing circuit 14 controls the serialshifting of the bits into register 13. As soon as register 13 containsall six binary bits, the input timing circuit 14 causes the six databits to be shifted out in parallel fashion into a buffer storage 15which, in the preferred embodiment, is comprised of a 133 stage shiftregister having six channels, whereby each associated stage of the sixchannels is adapted to store each six-bit binary word representing acharacter (i.e., number, letter or symbol). Each six-bit binary word isshifted in parallel into the first or loading stage of buffer storage 15and is advanced to the next stage as soon as the next six-bit binaryword is loaded, until the buffer 15 contains a total of I33 six-bitbinary characters (i.e., 132 six-bit characters and a dummy character).Shifting of the characters into buffer 15 is controlled by a shifterclock circuit 16, to be more fully described. As soon as the firstsix-bit binary character (dummy character) loaded into buffer 15 isshifted to the right-handmost stage (i.e., the l33rd stage) of thebuffer 15, the printer decodes this character as a print command toprint the first line of characters; The first six-bit binary character(i.e., the dummy character) which is loaded into buffer 15 is decoded asa print control signal as soon as it is shifted into the right-handmoststage so as to enable a print control circuit 17 which energizes thesolenoid 18 of a clutch mechanism to cause the carriage assembly (notshown), which has the printer head assembly mounted upon it, to moveacross the sheet from the left toward the right in order to perform theprinting operation. It should be understood that the motor which drivesthe carriage assembly is continuously energized, and it is the clutchmechanism 18 which selectively engages or disengages the carriageassembly from the motor.

Once the clutch solenoid is energized, the clutch mechanism causes thecarriage assembly to be mechanically linked to the energized'printermotor (not shown) and thereby cause the carriage assembly and theprinter head assembly to move from the left toward the right in order toprint one line of characters. As shown in schematic fashion, motor 19 iscontinuously energized and has its output drive shaft 20 coupled to adriven shaft 21 through clutch mechanism 22. Clutch solenoid 18 has itsarmature mechanically coupled to clutch mechanism 22, which mechanicallinkage is represented by dotted line 23a. When the clutch solenoid 18is energized, clutch mechanism 22 causes driven shaft 21 to be engagedwith drive shaft 20 through the clutch mechanism and thereby drive orrotate a driving roller 22. A belt 23 entrained about driving roller 24and a free-wheeling roller 24a has secured thereto the carriagemechanism 25 which supports the printinghead assembly 26. As soon as theclutch mechanism is engaged, belt 23 moves in the direction shown byarrow 27 to cause the carriage assembly 25 and printer assembly 26 tomove from the left toward the right. The movement of carriage 25 andprinting head assembly 26 is detected by a position detection device 28which includes an elongated strip having a pattern of alternating narrowtransparent and opaque segments provided on the strip. A light source 30emits light which is focused upon the rotating pattern by a focusinglens system 31. The light passing through the transparent slits ispicked up by a photocell device 32 to generate pulses representative ofthe selective light and dark areas provided on the pattern of the codewheel.

The output pulses of the electro-optical device 32 are applied to amatrix clock and decoder circuit 34 which generates signals at a firstoutput 34a coupled into the shifter clock circuit 16 which developspulses at its output 164 to cause shifting of the characters on aone-at-a-time basis from the output of character shifter circuit 15through lead 15:: into the input of a 64 character matrix circuit 35.

The other outputs 34b of matrix clock and decoder circuit 34 are appliedas sequential control pulses to the 5 X 7 matrix circuit 35 forcontrolling the particular vertical line of print solenoids utilized toprint a dot matrix-type character upon theprinted sheet. The outputs ofmatrix circuit 35 are applied through leads 35a to a plurality ofsolenoid driving circuits represented by block 36. Each of the drivingcircuits energizes an associated print solenoid 36a.

The printer of the present invention is of the dot matrix-type in whicheach character, letter or symbol is comprised of a plurality of dotsarranged in a 5 X 7 regular matrix in whichseven vertically aligned dotsare selectively printed in five vertical lines. FIG. 2 shows thecomposition of a few typical alpha-numeric characters, namely, thecharacters 1, 2, 3," 4, A, B, C and D. It can be seen that each of thesetypical characters are comprised of a plurality of dots arranged in aregular matrix of seven rows and five columns. Actual printing of thecharacters occurs in the following manner.

Let it be assumed that the character D is to be printed (see FIG. 2).The carriage in moving from the left toward the right will first printthe dots of column 1. All seven dots of the rows 1 through 7 will beprinted. The carriage assembly, which moves continuously during theprinting of a line, then moves toward the right until it is positionedat column 2. This position is detected by the photosensitive device 32which enables the dots of rows 1 and 7 to be printed. The carriageassembly then shifts to the column 3 location where the dots of rows 1and 7 are again printed when enabled by photocell 32. The carriageassembly then moves to the column 4 position, at which time the dots ofrows 2 and 6 are printed. Finally, the carriage assembly moves to thecolumn 5 position, at which time the dots of rows 3, 4 and 5 areprinted. It can thus be seen that the printer of the present inventionprints alpha-numeric characters of the dot matrix-type by selectivelyenergizing one or more of seven vertically aligned print wires as theprinter head carriage passes each column location to print a charactercomprised of selectively printed dots arranged over a five column byseven row matrix. Obviously, any other matrix size may be employed,depending only upon the needs of the user, without departing from thespirit or scope of the present invention.

The system of FIG. 1 is further provided with a special charactersdecoding circuit 37 which has its inputs selectively tied to the outputsof the serial-to-parallel circuit 13 and buffer 15 so as to decodespecial characters as and when they may be ready for loading into ortransfer out of buffer 15. The decoding circuitry 33 is comprised of aplurality of logic gating circuits for generating signals representativeof the special conditions such as a BUSY condition generated at itsoutput terminal 37a; a BELL condition generated at its output terminal37b; a DELETE signal generated at its output terminal 37c; a LINE feedsignal generated at its output terminal 37d; and a CARRIAGE RETURNsignal generated at its output terminal 37.

The BUSY signal which appears at output terminal 37a is generated whenbuffer 15 is fully loaded and a print mode is taking place. The BELLsignal appearing at output terminal 37b is generated by transmitting aBELL code whenever it is desired to gain the attention of the operator.The output energizes the BELL solenoid.

The LINE-FEED signal appearing at output terminal 37d is the signal thatis generated when a specific type of document is being printed in whicha substantial number of lines of the document are to be advanced beforethe next line of characters is printed upon the document. This outputsignal energizes the LINE FEED DRIVER and its associated solenoid toperform a LINE FEED operation.

THE CARRIAGE-RETURN signal appearing at output terminal 37a is generatedin instances where a line of print consists of less than the standard132 characters and it is, therefore, desired to advance to the next lineof characters to be printed before waiting until the carriage assemblyis advanced to its right-hand-most position. This signal causesenergization of the LINE FEED and RIBBON FEED drivers and theirassociated solenoids.

The PRIME logical circuit generates a signal at its output 37f whenevera lineof print has been completed or whenever a delete code is detected.

The limit switches LS-l and LS-2 detect the physical location of thecarriage assembly to control printing and carriage return operations.

The special character decoding circuitry 37, which has its output 37acoupled to the input of a buffer 13, causes the BUSY logic circuit toapply a voltage level to input line 11 which prevents theserial-to-parallel buffer 13 circuit from receiving characters until thelast line of characters loaded therein has been printed and the buffer15 is cleared.

FIG. 3 is a block diagram showing the input timing circuit 14 in greaterdetail. Before considering the circuitry and its operation, thefollowing brief description of the logic blocks employed will aid inunderstanding the system and its operation.

The logical gates which are utilized are comprised of Inverters, ANDgates, NAND gates, NOR gates and Exelusive-OR gates. An Inverter gatesuch as the gate 56 of FIG. 3 operates to provide a binary 1" level atits output when a binary 0 level is provided at its input. The binary llevel, in positive logic, is represented by +5 volts or high level.Binary 0 is represented by a 0 volt or ground level, also referred to asa low level. In the case where a binary l level input is applied to theInverter, a binary 0 level appears at the output.

An AND gate, such as the AND gate 231 of FIG. 7b generates a high leveloutput only when all of its inputs are high.

A NAND gate, such as the NAND gate 53, shown in FIG. 3, generates abinary "0 level at its output when all of its input terminals are inbinary 1" state and generates a binary 1 level at its output when one ormore of its inputs are at binary l level.

A NOR gate, such as the NOR gate 57, shown in FIG. 3, generates a binary1 level output when all of its inputs are at binary 0" and generates abinary 0" level at its output when one or more of its inputs are atbinary l level.

An Exclusive-OR gate, such as, for example, the Exclusive-OR gate 228shown in FIG. 7b, generates a binary 0 level at its output when all ofits inputs are at binary l or when all of its inputs are at binary 0. Inthe case where at least two of its inputs are at different binarylevels, the output of the Exclusive-OR gate is at binary l level. i

The J-K flip-flop such as, for example, the flip-flop 58 shown in FIG. 3is provided vith .I and K inputs 58a and 58c, respectively; Q and Qoutputs 58d and 5842, respectively; a clock input 58b; a clear input 58fand a preset input 58g. The normal states of outputs 58d and 58e aresuch that they are complements of one another. To set output terminal58d at a high level, a signal which is high when applied to input 580when the clock pulse signal at terminal 58b is high determines thesetting of output terminal 58d. The actual switching of the signal levelat terminal 58d, however, occurs when the clock pulse level at input 58bgoes low. To set output terminal 58:: to a high level, a high level atinput terminal 58c when the clock pulse level at 58b is high, willdetermine the setting of output terminal 58c. The actual change of stateof the .l-K flip-flop occurs, however, when the clock pulse level atinput terminal 58b goes low. A low level input at clear terminal 58fsets the output (58d) low. A low level input at preset terminal 583 setsQ high. The clear and preset inputs do not require the presence of aclock pulse.

The input timing circuit is comprised of an oscillator 50 generatingmicrosecond pulses at a rate of I00 kilocycles. The output of oscillator50 is coupled to a bistable flip-flop circuit 52 through inverter 51.Flipflop 52 divides the output of oscillator 50 to thereby generatemicrosecond pulses at a rate of-SO kilocycles at the output 52d ofbistable 51 hereinafter referred to as the CLOCK. Inputs 52a and 52c aremaintained at binary I. The output 52d of bistable 52 is coupled to oneinput 53a of NAND gate 53 whose output is coupled to the input of afour-stage binary Timing Counter 54 having output terminals TC,, TC,,TC, and TC; for each of the four stages. NAND gate 53 transfers clockpulses totiming counter 54 when switch 55 is opened to impose a binary llevel upon NAND gate 53 and thereby enable pulses from oscillator 50 tobe passed to the input of timing counter 54. When switch 55 is closed, abinary 0" level is applied to gate 53 to inhibit oscillator pulses fromreaching counter 54. The closing of switch 55 occurs when data ispresented to the printer system in parallel fashion, which operatingmode will be more fully described. I

Timing Counter 54 is inhibited from counting until its input terminals54d and 54b'are both high to cause the counter to be reset and begincounting under control of the Clock output 52a. The BUSY signal is highwhen the 133 stage buffer of the printer system is not completelyloaded. The generation of this signal will be more fully described inconnection with FIG. 6. The TL signal is low prior to the initiation ofthe next binary bit. Under this condition, NAND gate 59 applies a binaryl level signal to input terminal 54!). Upon the initiation of the nextbit, the TL signal goes high causing the output of NAND gate 59 to golow. The HTC signal is high when the TC4 and TC8 outputs of timingcounter 54 are high causing the I-ITC signal appearing at the outputterminal of 58a to go high. This causes Timing Counter 54 to be resetand start a new count.

As soon as the next binary bit is received, the TL signal goes highcausing the output of NAND gate 59 to go low. Simultaneously therewith,the TL signal is applied to input 58a of J-K flip-flop 58 causing theHTC signal at output terminal 58d to go high upon the occurrence of thenext TCl signal from Timing Counter 54 which is applied to input termirtl 58b. This causes the output terminal 58 (the I-ITC signal) to gohigh, thereby preventing the Timing Counter 54 from being reset untilthe next time the TL input to gate 59 goes high and simultaneouslytherewith until the TC4 and TC8 outputs are high.

.I-K flip-flop 58 is cleared (causing output 58d to go low) when eitherthe PRIME or the BUSY signal, or both, go high, in a manner to be morefully described.

The outputs of timing counter 54 are further coupled through invertercircuits 55;s55 d, resgctively lo develop the output signals TC,, TC,,TC, and TC,,, respectively.

The output terminals TC, and TC, of Inverters 55c and 55d are coupled tothe inputs of NOR gate 57 whose output is coupled to one input terminal580 of J K flip-flop circuit 58. Input terminals 58a and 58b are coupledto the outputs of the input buffer line 120 (see FIG. 1) and to the TC,output of timing counter 54, respectively. Output terminal 58e iscoupled to one reset-enable input terminal 54a of timing counter 54. Theremaining reset-enable input terminal 54b is coupled to the output ofNAND gate 59 whose inputs are coupled to the TL output of Inverter 73shown in FIG.

FIG. 5 shows waveforms representing the system timing. Waveform 52drepresents the clock output 52a shown in FIG. 3. Although the output ofoscillator 50 is not shown, it should be understood that the output ofoscillator 50 is twice the frequency of clock 52. Waveforms TC throughTC; represent the output waveforms appearing at these associatedterminals provided by Timing Counter 54.

Waveform TL represents the incoming binary information applied to inputline 11, shown in FIGS. 1 and 6, which binary data is applied to inputline 11 in serial fashion. One unique feature of the present inventionis the fact that binary bits are generated during 320 microsecondintervals and that binary 0 and binary 1 bits are distinguished from oneanother during each 320 microsecond interval by the time interval duringwhich each pulse is high" (i.e., binary l level). For example, let it beassumed that the first binary bit applied to line 11 is a binary 1 bit.At time t the signal level of this signal is low, and it remains low fora 200 microseconds interval, at which time the signal level goes highand remains high for the remaining 120 microseconds. The next bittransmitted which is a binary 0" bit, has its signal level low for atime duration of microseconds, at which time the signal level abruptlygoes high and remains high for the remaining 240 microseconds of the bittransmission interval of 320 microseconds.

The binary bits applied to the input line 11 are inverted by Invertermeans 73 to be more fully described in connection with FIG. 6. Since theinitial portion of either a binary 0 or a binary l level bit is low, theaforementioned Inverter inverts the signal to apply a high level toinput terminal 58a of flip-flop 58. As soon as the TCl output of TimingCounter 54 goes low, a high level input is applied to input terminal 58bof flipflop 58 causing the output terminal 58d of bistable flipflop 58to go high, as shown by the waveform .I-ITC. The signal level at outpi ttermin al58d remains high until the output levels at TC, and TC ofcounter 52 go high (which occurs 240 microseconds after the initiationof a binary bit interval), which causes the output of NOR gate 57(coupled to the TC4 and TC8 outputs of Inverters 55c and 55d) to gohigh, applying a high level input to terminal 58c of the bistableflip-flop,causing output terminal 58d to go low upon the occurrence ofthe next TCl signal. Output 58d remains at the low level for theremaining 80 microseconds of the first 320 microseconds binary bitinterval and goes high again when the next binary bit transmitted (seeline TL) is applied to input 58b followed by the next negativetransition of output TCL (which occurs 330 microseconds after time i=)as is shown by the waveform 58d of FIG. 5.

FIG. 4 is a block diagram showing the Control Counter circuitry includedwithin input timing circuit 14 of FIG. 1, and is comprised of afour-stage binary Control Counter 60 which derives its input at 60a fromthe Clock output 52d, shown in FIG. 3. The four stages of the countereach have an associated output CC,, CC,, CC and CC which outputs areutilized to develop further timing information. NAND gate 62 has itsthree input terminals coupled to the CC,, CC. and CC output terminals ofCounter 60. A second NAND gate 63 has its input terminals coupled to theinput line (TL) 11 of FIGS. 1 and 6, the BUSY line of Inverter 72 (seeFIG. 6), and the ETC output terminal 58a of the flip-flop 58 shown inFIG. 3. The outputs of NAND gates 62 and 63 are coupled to correspondinginputs of a NAND gate 64 whose output is coupled to one input terminal65c of a bistable flip-flop circuit 65 whose remaining input terminals65a and 65 b are respectively coupled to the TC8 output terminal ofCounter 52, shown in FIG. 3, and to the Clock output 52d of bistable 52.It can be seen from the waveforms shown in the timing diagram of FIG. 5that, when TC8 goes positive and when the next negative transition ofthe clock output is generated (180 microseconds after time i=0), theoutput at terminal 65d goes (RTC) high, as shown by waveform 65d in FIG.5. Resetting of counter 60 to permit counting is caused by a low RTCsignal and +5 volts at input terminals 60c and 60b, respectively. TheRTC output remains high until either one of two conditions occur. If allof the inputs of either NAND gate 62 or NAND gate 63 go high then theoutput of one of the NAND gates 62 or 63 goes low, causing the output ofNAND gate 64 to go high to thereby reset the level at output terminal65d to the low level. The output of gate 63 normally goes low at thebeginning of each bit. However, either an error in transmission or astop pulse will enable counter 60 to time out whereby outputs CC2, CC4and CC8 cause gate 62 to go low and generate EOC which is utilized in amanner to be more fully described in connection with FIGS. 6 and 7 toclear the serial-to-parallel converter 70 (see FIG. 7) before it canshift an invalid character into 133 character shifter 136 or to clearconverter 70 prior to the receipt of the next coded character.

FIG. 6 is a detailed block diagram of the serial-toparallel convertercircuit I3 shown in FIG. I which is comprised of a nine-stage shiftregister 70 having an input line 70a, output lines TRO through TR8 and ashift pulse line 70b.

The incoming stream of binary serial information is coupled to line TLand applied to the input line 70a incoming data stream to pass to theserial-to-parallel converter circuit 70. In the case where the 133 stageshift register is fully loaded with coded characters and is therebyoperating to print these characters, the BUSY signal applied to theinput of Inverter 73 is high preventing further loading of themultistage shift register. As soon as the multistage shift register isfully loaded, the signals applied to the input of Nand gate 71 (whichwill be more fully described hereinbelow) cause the output of Nand gate71 to go low, which low level is inverted by Inverter 72 to block thepassage of any further binary information to the serial to parallelconverter circuit 70. Shift pulses for shifting the serial datapresented to input line 70a are controlled by the circuits comprised ofNor gate 74, NAND gate 75 and Inverter 76 which operate in a manner tobe more fully described.

The operation of the timing circuits and shift register, as shown in IfIGS. 3-6 and 6a, is as follows:

The input line TL goes low (i.e., binary "0 at the beginning of eachbinary bit. In the case of a binary l, the signal remains low for 200microseconds and is abruptly changed to binary 1 level (i.e., goes high)where it remains high for the remaining microseconds. At the tenninationof the bit interval, the signal level again goes low (i.e., binary 0).In the case of a binary 0" bit, the signal level remains low for aperiod of 80 microseconds and abruptly goes high (i.e., becomes binaryl) and remains high for the remaining microseconds of the bit interval.Considering waveform 73a in FIG. 5 which represents the dag applied toinput 73a of Inverter 73 shown in FIG. 6, TL goes low at time t=0. Thiscondition is applied to input terminal 56b of J-K flip-flop 58. Upon theapplication of the-next TCl pulse from counter 54 (see waveform 54 ofFIG. 5) output terminal 58d goes high (see waveform 58d of FIG. 5) andremains high until TC4 and TC8 (see waveforms 52c and 52d of FIG. 5) areboth high which occurs 240 microseconds after time t=0 at which time theclock pulse TC! is low causing the output of terminal 58d to go low andthe output at terminal 58c to go high. Counter 54 is reset at thebeginning of each bit interval as a result ithe signal TL and the BUSYsignal being high and I-ITC (i.e., the output of terminal 56c) beinghigh. Bits are loaded into the shift register 70 when the shift pulsefor the serialto-parallel converter 7%) is generated. The shift pulse isgenerated I60 microseconds after time i=0 by means of gates 74-76. NORgate 74 develops a b inary 1 output when both the BUSY signal and TC8are both low (i.e., binary 0). This binary I level output is applied toone input of NAND gate 75 which develops a binaryiQ: le w l output w henthe output of Nor gate 74 and TCI, TC2, and TC4 are all binary 1" (i.e.,when TCI, TC2, 'IC and TC8 are low). As can be seen from waveforms52a-52c, this occurs microseconds after time i=0. This output level isinverted by Inverter circuit 76 to apply a binary l level signal toshift-pulse input terminal 70b to shift the binary state of the bit intoshift register 70 wherein the status of the bit is established by thelevel'of the TL signal during the interval in which the output ofInverter 76 is high.

Counter 60 is inhibited from initiating a counting operation until TC8goes high. This level is applied to input terminal 65b of J-K flip-flop65 causing output terminal 65d to go high and output terminal 651: to golow. Output terminal 65c is coupled to input terminal 60c of counter 60enabling the counter to be stepped under control of clock signal 52a.Flip-flop 65 is reset by means of input signals applied to NAND gates62, 63 and 64 at atime when either CC8, CC4, CC2 or TL, HTC, and BUSYsignals are all high, thereby causing output terminals 65:: and 65d togo high and low, respectively, upon the occurrence of the next outputpulse from the oscillator 52 which is applied to 65c. This operation canalso be seen from a consideration of waveforms 60d, 60e, 60f, 73a and58d of FIG. 5. Bistable flip-flop 65 will be reset to reset the count ofcounter 60 in'the case when the output of either NAND gate 62 or 63 isbinary 0. The output of NAND gate 62 will go low when the CC8, CC4 andCC2 inputs are all high which will occur 160 microseconds after theenablement of counter 60 to reset and beging counting. Since counter 60is not enabled until 160 microseconds after the initiation of any bitinterval, resetting of the counter under control of the CC8, CC4 and CC2outputs will only occur if the bit interval erroneously is longer thanthe allotted 320 microseconds. Counter 60 will thus be reset if the TC,HTC and BUSY signals are in binary 1 state which occurs at the beginningof each bit interval, if the bit interval is of correct length. Counter60 is permitted to time out" at the end of a character due to thetransmission of a 640 microsecond pulse which is transmitted at the endof each character (see FIG. The EOC signal generated by gate 62 of FIG.4 is employed in thelogic of FIG. 7a to clear serial-to-parallelconverter 70 after each character is loaded into buffer from shifter 70.

THE POSITION CONTROL APPARATUS The exact positioning of the printer headassembly is determined by the position control apparatus shown in FIG.11 which consists of an elongated opaque mylar strip 160 having aprinted pattern thereon provided with a plurality of relatively thintransparent slits 160a uniformly spaced along the mylar strip. A lightsource 164 positioned behind the strip and a photodetector 162 aremounted upon the printer head assembly carriage to be movable therewith.The mylar strip is mounted in a stationary fashion and extends the widthof the printer platen. In one preferred embodiment,

NAND gate is thereby enabled to pass pulses to the input of a pulsewidening circuit 165 which may, for example, be a one-shot multivibratorto generate a pulse of 400 microseconds pulse duration. The outputsignal at 1650 referred to as a Strobe pulse, is applied to the inputterminal 166a of a divide-by-six counter 166 having three outputs166b-166d. An inhibit (CIR) pulse is derived from the output terminal144d of circuit 144 shown in FIG. 9d (which is derived in a manner to bemore fully described) and applied to input l66e in order to preventcounter 166 from generating output signals during the time in which thecarriage assembly is moving in the line-retum direction. Outputs166b-166d are coupled to Inverter circuits 167-169, respectively, tomake available both the output levels at output terminals 166b-166d andtheir complements.

The output signals at terminals 166b-166d and their complements areselectively applied to the input terminals of a group of NANDgates170-175, shown in FIG. 10b. The output terminals 166b-166d are soconnected as to develop output signals which operate the 64 charactergenerator 5' X 7 matrix 178 in a sequential fashion. For example, NANDgate 170 has its inputs coupled to the outputs 167a-169a of invertercircuits 167-469, respectively, as well as the Strobe output 1650 ofcircuit 165. As soon as all of these outputs are in binary "1 state,indicating an initiation of the printing operation in which the printerhead assembly is positioned at the extreme left-hand end of the nextline to be printed, the output of NAND gate 170 generates a low levelwhich is inverted by Inverter 176a to develop the DCWq': signal which isutilized in the circuit of FlG. 7b to shift the next coded character inbuffer 15 into the output stage.

NAND gate 171 develops a binary 0" level signal when all of the signalsat output terminals 166b, 1680, 169a and the Strobe output 165a are allat binary 1 level (i.e., high). This output is inverted twice byInverter circuits 176!) and 177a, respectively, to couple an outputsignal to input terminal 178a of the character generator circuit 178. Itshould be noted that this occurs upon the accumulation of the firstcount in counter 166. The application of this signal to input terminal178a cooperates with the coded character binary input levels applied toinput terminals 178f-l78n, respectively, (and shifted into the outputstage of buffer 15 by the DCW4 signal) to selectively energize 132 slotsare positioned across the length of strip 160 in one or more of theoutput terminals 178a-178a which control the print solenoids to beenergized during the printing of the left-hand most column of the firstcharacter. Each of the output tenninals 178n-178u is coupled to a drivercircuit. Only one of these driver circuits has been shown in FIG. 11bfor purposes of simplicity, it being understood that the remainingcircuits are substantially identical in design and function. Outputterminal 178" is coupled to the base of transistor T, through resistor RT, is rendered conductive when the level at output terminal 178:: goeshigh to cause its emitter electrode to go high and thereby rendertransistors T, and T conductive to energize print solenoid SOLJ. foroperating its associated printwire. A print solenoid and printer headassembly which has been used to great advantage in the printer system ofthe present invention is set forth in detail in application Ser. No.37,815, filed May 15, 1970 and assigned to the assignee of the presentinvention. Of course, any other print assembly may be used, if desired.

The remaining gates 172-175 operate in a similar fashion to provideoutput signals occurring in time sequence to thereby energize the printwires of the solenoids in time sequence as the printing head assemblymoves (at a substantially constant rate) from the left toward the rightto selectively make contact with the paper document and thereby printselected dots upon the document to form the appropriate character.

Matrix 178, may, for example, be a MOS-LSI character generator of thetype 2A4l03 manufactured by the Texas Instrument Corporation.

CARRIAGE RETURN (CR) GENERATING CIRCUIT NAND gate 101 of FIG. 80 goes tobinary when the coded character shifted into the serial-to-parallelconverter circuit 70 (in binary form) is 1 101 1000 to indicate that acarriage return operation is requested. Inverter 102 provides a binary 1output (CR signal) which is used to generate the Special STRS and STR6signals to be more fully described in connection with FIGS. 6 and 7b.The low output of NAND gate 101 is coupled to one input of NOR gate 103to cause its output to go high upon the receipt of a low level signalfrom the output 222d (FCCLK) of J-K flip-flopshown in FIG. 7. Thisoutput signal is applied to the input 104a of J-K flip-flop 104 fordeveloping a high level signal when the next pulse from oscillator 50(seeiG. 3) goes negative. The complementary output (RCR) at terminal104e is applied to one input to NOR GATE 105 and as one input to NANDgate 71 of FI G. 6. In the presence of a carriage return request, RCRgoes low disabling gate 71 to prevent data from being fed toserial-to-parallel converter 70 ofl IG. 6. In the absence of a carriagereturn request, RCR goes high enabling gate 71 to go low which conditionis inverted by Inverter 72 to enable data to enter serial-to-parallelconverter 70.

Flip-flop 104 is reset upon the occurrence of the next oscillator pulsewhen either the outputof NAND gate 101 goes high or when the output 222dof flip-flop 222 (see FIG. 7b) goes high.

NOR gate 105 is low when either RCR is high (absence of carriage return)or when the output of NOR gate 247 in FIG. 7 goes high (theserial-to-parallel converter is cleared as a result of either an invalidbit or character or receipt of an end of character pulse). When theinputs are both low, NOR gate 105 causes output 106d of J-K flip-flop106 to go high during the next negative transition of oscillator 50(FIG. 3). Output 106d (ZBCR) is applied to one input of AND gate 233shown in FIG. 7b to rapidly shift the characters of FIG. 7a to permitclearing of serial-to-parallel converter during the carriage returnoperation.

BUFFER CARRIAGE RETURN (DCR) CIRCUIT The circuit of FIG. 8b is comprisedof NAND gate 107 which is coupled to selected terminals of the outputstage of 133 character buffer 180 shown in FIG. 10. Gate 10 develops abinary "0 level output (DCR) when the character contained in the outputstage of the shifter buffer 180 (in binary form) is lllllO whichrepresents a carriage return operation called for by buffer 180. Thisoutput (DCR) is inverted by gate 108 driving the output 109d (RDCR) highof flip flop 109 when the next oscillator pulse goes negative. RDCRdeactivates the forward clutch driver of FIG. 9b and activates thereverse clutch drive of FIG. 90. (in a manner to be more fullydescribed) when high. Output terminals 109d (RDCR) and 109e (RDCR) golow and high, respectively, after the carriage return function iscompleted, under control of the PRIME signal developed by the circuit ofFIG. 8f (to be more fully described hereinbelow).

BUFFER FULL (TBF) GENERATING CIRCUIT FIG. is comprised of three NORgates 110-112 having their input terminals connected to selected outputsof the output stage of 133 character buffer 180. The outputs of- NORgates 110-112 go high when the output terminals TB are all in binary 0state causing the output 113a (TBF) of NAND gate 113 to go low, whichMition is inverted bygwerter gate 1 14. When the TBF output is low(i.e., TBF is high) J-K 106 of FIG. 8a is reset to prevent the buffer180 from being cleared during loading. 'TBF also enables the generationof shift pulses (FIG. 7b) to sequentially shift the data stored inbuffer 180 into the character generator 156 (FIG. 11b) and is utilizedin FIG. 90 to enable the forward clutch to be energized to move theprinter head assembly.

CARRIAGE POSITION DETERMINING CIRCUIT FIG. 8d sho'wsthe circuitry, whichtogether with the circuitry of FIGS. 9a-9c functions to control thedirection of movement of the printer head assembly carriage. As shown inFIG. 8d, limit switch LS1 is physically engaged by the carriage assemblyand closes when the printer head carriage reaches its left-hand mostposition. This low level is inverted by Inverter 115 to set the output116d (RTP) of .l-K flip-flop 116 high when the oscillator output (50 ofFIG. 3) goes negative. RTP goes low when the first character is printedunder control of signal DCWS from inverter 176f of FIG. 10b.

I RTP may also be driven to a low level when PRIME is loaded into the133 character buffer of FIG. 10a to low which occurs upon the initiationof a carriage return operation.

BELL GENERATING CIRCUIT FIG. 8c shows the logical circuitry forgenerating a Bell signal and is comprised of a NAND gate 1 17 whoseoutput 117a goes high when the binary bit positions TRO-TR7 of the codedcharacter in the serial-to-parallel converter circuit 70 is (in binaryform) llll0000. This output is applied to one-shot multivibrator 118 toenergize-a bell or alarm solenoid 119 for approximately

1. A high speed printer of the dot-matrix type for forming a pluralityof spaced dot patterns upon the surface of a document, comprising: amovable print assembly for sequentially forming vertically aligned dotpatterns at closely spaced intervals to generate each symbol; means formoving said assembly in a first direction across a document at asubstantially constant rate of speed to cause each character to beprinted in a sequential fashion; holding means receiving said documentfor preventing movement of said document in said first direction; saidprint assembly including slender movable impact members having theirimpact ends positioned a small spaced distance from said document;control means for selectively conditioning the impact members to controlthe next vertical dot pattern to be formed; an elongated stationarymounted code strip extending substantially parallel to both the printingsurface of said document and the line of travel of said assembly andbeing positioned adjacent said print assembly, said strip being providedwith a plurality of narrow indicia, which are located at each and everyprint position at which said assembly is capable of printing; said printassembly including means movable therewith and positioned adjacent saidstrip for scanning said strip to detect the presence of each successIveindicia as said assembly moves in said first direction to enable thoseimpact members conditioned by said control means to print a vertical dotpattern only when that indicia associated with the next print positionis detected and regardless of the rate of movement or any change in therate of movement of said print assembly in said first direction.
 2. Theprinter of claim 1, wherein all of said indicia are of a first color andare located at spaced intervals along said strip which is of a secondcolor which is different from said first color; said detecting meanscomprising: a light source; means for directing the light rays from saidlight source to impinge upon the surface of said strip containing saidindicia; and a light sensitive means for generating an output signalonly when the light rays impinge upon one of said indicia; said outputsignals being coupled to said control means to enable said control meansto operate said assembly.
 3. The printer of claim 1, wherein said stripis formed of a thin strip of flexible material; said indicia beingcomprised of a plurality of narrow light-transparent slits arranged atspaced intervals along said strip and being parallel to one another;said print assembly further including: a light source for directinglight rays to impinge upon said strip and being positioned to one sideof said strip; a light sensitive means mounted upon said assembly andbeing positioned upon the opposite side of said strip for generating anoutput signal only when said light rays pass through one of said indiciaand are picked up by said light sensitive means; said output signalsbeing adapted to enable said control means to operate said assembly. 4.The printer of claim 1 further comprising: means for receiving codedinformation signals representing the symbols to be printed; meanscoupled to said receiving means for storing a group of said informationsignals sufficient to print any predetermined number of charactersand/or symbols up to a full line of print; storage detecting meanscoupled to said storing means for detecting the completion of thestoring of said information signals to initiate a printing operation;said control means being coupled to said storage means and responsive tosaid storage detecting means.
 5. A high speed printer of the dot-matrixtype comprising: a movable carriage movable between a ready to printposition and an end of print position, said carriage having a printerhead assembly for sequentially forming vertical columns of dots torepresent characters or other symbols; shift register means for storinga plurality of groups of binary signals, each of said groupsrepresenting a character; means for sequentially shifting each group ofsignals into said register; first drive means for moving said carriagein a print direction; second drive means for moving said carriage in acarriage return direction opposite said print direction; means fordetecting the return of said carriage to said ready-to-print positionfor loading a print control code into said register preparatory toreceipt of said group of signals; control means coupled between theoutput of said register and said printer head assembly for controllingthe operation of said printer head assembly; print control means coupledto the output of said register to enable said control means to initiatea printing operation when said print control code appears at the outputof said register.
 6. The printer of claim 5, further comprising inputmeans comprised of means for receiving each group of signals in serialfashion and loading each group of signals into said register in parallelfashion.
 7. The printer of claim 6, further comprising means fordetecting the initiation of each signal; means responsive to saiddetecting means for enabling each signal to be loaded into said inputmeans a predetermined time after said initiation of each signal wherebythe leveL of the signal at said predetermined time determines the binarystate of the signal which is loaded into said input means.
 8. Theprinter of claim 6 wherein each binary bit is of equal length andwherein the beginning of each bit is distinguished from the end of theprevious bit by a difference in signal level and wherein a first portionof a bit interval of a first binary state is greater in length than afirst portion of a bit of the opposite binary state; timing meansinitiated by the start of each bit to generate a timing signal apredetermined time period longer than the interval of a bit, said timingmeans adapted to be reset in the presence of each newly received bit tobegin a new cycle before generating said timing signal; means coupled tosaid timing means to clear said serial to parallel converter uponreceipt of a timing signal.
 9. The printer of claim 6 wherein saidenabling means further comprises second timing means coupled to saidinput means for generating an output pulse a predetermined time afterthe beginning of each input interval which predetermined interval islonger than the interval of the first portion of said first binary stateand shorter than the interval of the first portion of said oppositebinary state; means coupled to said second timing means and said inputmeans to shift each bit into said register whereby the state of the bitshifted into said register is determined by the state of the bit at thetime said output pulse is generated.
 10. The printer of claim 6, furthercomprising means coupled to said register means for preventing theloading of groups of signals into said input means when said printcontrol code appears at the output of said register.
 11. The printer ofclaim 6, further comprising shift control means coupled between saidshift means and said input means for shifting the groups of signalspreviously loaded into said register toward the output thereof when saidshift control means detects the presence of a print control code in saidinput means; said print control means including means for disabling saidshift means when a print control signal appears in the output of saidregister.
 12. The printer of claim 6, further comprising means fordetermining the duration of each signal; means coupled to saiddetermining means for clearing said input means prior to shifting of thecontents of said input means to said register when any one of the signalintervals are of non-uniform length.
 13. The printer of claim 12,wherein each group of signals is comprised of a plurality of datasignals of equal time duration followed by a stop signal of a timeduration greater than said data signals; means for enabling said shiftmeans prior to the activation of said determining means to enable thecontents of said input means to be shifted into said register prior tothe clearing of said input means which prepares the input means forreceipt of the next group of signals.
 14. The printer of claim 13,wherein each group of data signals is preceded by a start signal of apredetermined binary state and having a time duration equal to said datasignals; means for detecting the state of said start signal when a groupof signals has been loaded into said input means to clear said inputmeans prior to shifting the contents of said input means into saidregister when the binary state of said start signal is opposite saidpredetermined binary state.
 15. The printer of claim 5, furthercomprising: switch means operable to generate a ready to print signalwhen said carriage is in said ready-to-print position; said printcontrol means including means responsive to said switch means to preventa printing operation until said carriage is in said ready-to-printposition; means coupled between said print control means and said firstdrive means to energize said first drive means when said carriage is inthe ready-to-print position and said print control code appears at theoutput of said register.
 16. The printer of claim 15, wherein said meansfor energizing said first drive means is further coupled to said shiftmeans for shifting said print control out of said register and forshifting the first group of signals representing a character or symbolto be printed into the output of the register.
 17. The printer of claim5, further comprising switch means operable to generate a carriagereturn signal when said carriage is in said end of print position; meansresponsive to said carriage return position for deenergizing said firstdrive means and for energizing said second drive means.
 18. The printerof claim 17, wherein said second drive means moves said carriage at afaster speed in the carriage return direction than the speed of saidcarriage in the print direction.
 19. The printer of claim 17, furthercomprising means coupled to said means for energizing said second drivemeans for clearing the contents of said register during a carriagereturn operation.
 20. The printer of claim 5, further comprising: anelongated stationary code strip extending substantially parallel to theline of travel of said assembly, said strip being provided with aplurality of narrow indicia each designating a print position; saidassembly including means for detecting the presence of each indicia assaid assembly moves in said first direction to prevent the assembly fromprinting each vertical dot pattern until its associated indicia isdetected.
 21. The printer of claim 20, wherein said control means isfurther comprised of a matrix code generator for receiving a group ofsaid data signals for converting said group of data signals into aplurality of groups of print signals; means coupled to the positiondetecting means for sequentially coupling said each of said groups ofprint signals to said printer head assembly during succeeding printpositions.
 22. The printer of claim 21, wherein said printer headassembly is comprised of: a plurality of print wires having theirforward ends adjacent a paper document to be printed upon and havingtheir rearward ends coupled to and driven by an associated printsolenoid; each of said solenoids being coupled to receive an associatedone of said print signals; said forward ends being arranged along animaginary straight line.
 23. The printer of claim 21, further comprisingmeans coupled to said indicia detection means for operating said shiftmeans to shift the next group of signals into the output of saidregister after the last group of print signals has been coupled to saidprinter head assembly.